1. Field of the Invention
The present invention relates to a semiconductor device for charging electric power generated by electric power generation means into electricity storage means, and driving a drive circuit by the generated electric power or the stored electric power, and more specifically, to an overcharge prevention circuit for preventing overcharge into electricity storage means.
2. Description of the Related Art
FIG. 3 is a circuit diagram illustrating a semiconductor device including a conventional overcharge prevention circuit. The semiconductor device including the conventional overcharge prevention circuit includes a solar battery 31 as electric power generation means, a secondary battery 32 as electricity storage means, a diode 33 as a backflow prevention circuit, an overcharge detection circuit 34, and an NMOS transistor 35 as an overcharge prevention switch.
A negative terminal of the solar battery 31 is connected to a low-potential side power source VSS. A positive terminal of the solar battery 31 is connected to an electric power generation source VSOL. A negative terminal of the secondary battery 32 is connected to the low-potential side power source VSS. A positive terminal of the secondary battery 32 is connected to an electricity storage power source VBAT. The diode 33 has an anode terminal connected to the electric power generation source VSOL and a cathode terminal connected to the electricity storage power source VBAT. The overcharge detection circuit 34 is driven between the electricity storage power source VBAT and the low-potential side power source VSS. An output node VDET outputs a High (VBAT) level when VBAT is a predetermined voltage VLIM or more, and outputs a Low (VSS) level when VBAT is less than the predetermined voltage VLIM. The NMOS transistor 35 has a drain terminal connected to the electric power generation source VSOL, a source terminal and a back gate terminal connected to the low-potential side power source VSS, and a gate terminal connected to an output terminal of the overcharge detection circuit 34.
Next, an operation of the semiconductor device including the conventional overcharge prevention circuit is described. FIG. 4 is an operational explanatory diagram of the semiconductor device including the conventional overcharge prevention circuit. A forward voltage of the diode 33 is represented by VF.
In a period of t0 to t1, the solar battery 31 does not generate electric power or the amount of generated electric power of the solar battery 31 is small, and the relationship of VSOL<VBAT+VF is established. In this case, the diode 33 is biased in the reverse direction, and a backflow current does not flow from VBAT to VSOL (non-charged state).
In a period of t1 to t2, the amount of generated electric power of the solar battery 31 is large so that a potential of VSOL increases sufficiently, and the relationship of VSOL>VBAT+VF is established. In this case, the diode 33 is biased in the forward direction, and the charge from VSOL, to VBAT is performed (charged state).
In a period after t2, VBAT has exceeded the predetermined voltage VLIM, and the output VDET of the overcharge detection circuit 34 becomes the High level (VBAT), and hence the NMOS transistor 35 is turned ON (overcharged state). In this case, a generated current of the solar battery 31 is discharged to VSS via the NMOS transistor 35, and hence a potential of VBAT becomes substantially equal to that of VSS.
In this state, VBAT≈VSS is established regardless of the presence or absence of the generated electric power of the solar battery 31. Accordingly, there has been a problem in that the generated electric power of the solar battery cannot be detected and therefore brightness determination cannot be performed.
Japanese Patent Application Laid-open No. 2002-10518 is known as the invention which has been made in view of the above-mentioned problem. FIG. 5 illustrates a schematic diagram thereof.
A semiconductor device including a conventional overcharge prevention circuit illustrated in FIG. 5 includes a solar battery 51 as electric power generation means, a secondary battery 52 as electricity storage means, a diode 53 as a backflow prevention circuit, an overcharge detection circuit 54, an NMOS transistor 55 as an overcharge prevention switch, a reference voltage generation circuit 56, and a comparator circuit 57. A negative terminal of the solar battery 51 is connected to a low-potential side power source VSS. A positive terminal of the solar battery 51 is connected to an electric power generation source VSOL. A negative terminal of the secondary battery 52 is connected to the low-potential side power source VSS. A positive terminal of the secondary battery 52 is connected to an electricity storage power source VBAT.
The diode 53 has an anode terminal connected to the electric power generation source VSOL and a cathode terminal connected to the electricity storage power source VBAT. The overcharge detection circuit 54 is driven between the electricity storage power source VBAT and the low-potential side power source VSS. An output node VDET outputs a High (VBAT) level when VBAT is a predetermined voltage VLIM or more, and outputs a Low (VSS) level when VBAT is less than the predetermined voltage VLIM. The NMOS transistor 55 has a drain terminal connected to the electric power generation source VSOL, a source terminal and a back gate terminal connected to the low-potential side power source VSS, and a gate terminal connected to an output node VGN of the comparator circuit 57. The reference voltage generation circuit 56 is driven between the electricity storage power source VBAT and the low-potential side power source VSS, and outputs a constant voltage VREF. The comparator circuit 57 is driven between the electricity storage power source VBAT and the low-potential side power source VSS. The comparator circuit 57 has a positive input terminal connected to the electric power generation source VSOL and a negative input terminal connected to the output node VREF of the reference voltage generation circuit 56. The output node VGN of the comparator circuit 57 outputs the High (VBAT) level in the case of VSOL>VREF, and outputs the Low (VSS) level in the case of VSOL<VREF. The comparator circuit 57 has an enable terminal connected to the output VDET of the overcharge detection circuit 54. The comparator circuit 57 is in an operating state when VDET is High and a non-operating state when VDET is Low.
Next, the operation of the semiconductor device including the conventional overcharge prevention circuit illustrated in FIG. 5 is described.
FIG. 6 is an operational explanatory diagram of the semiconductor device including the conventional overcharge prevention circuit. A forward voltage of the diode 53 is represented by VF.
The operation in a non-charged state corresponding to a period of t0 to t1 and a charged state corresponding to a period of t1 to t2 is the same as in FIG. 4.
In a period after t2, VBAT has exceeded the predetermined voltage VLIM, and the output VDET of the overcharge detection circuit 54 becomes the High level (VBAT), and hence the comparator circuit 57 becomes the operating state (overcharged state). Due to a negative feedback operation of the comparator circuit 57 and the NMOS transistor 55, a potential of VSOL becomes equal to a potential of VREF.
In this case, the solar battery 51 can output the potential in the range from the potential of VSS to the potential of VREF in accordance with the amount of generated electric power, and hence brightness determination can also be performed easily.
However, in the semiconductor device including the overcharge prevention circuit illustrated in FIG. 5, as compared to the semiconductor device including the overcharge prevention circuit illustrated in FIG. 3, the reference voltage generation circuit 56 and the comparator circuit 57 are additionally needed in order to add a clamp function. Therefore, there is a problem in that the number of elements constituting the circuit increases, and the chip area increases.
Further, the reference voltage generation circuit 56 and the comparator circuit 57 are driven between the electricity storage power source VBAT and the low-potential side power source VSS. Therefore, there is a problem in that, even if electric power is charged in the electricity storage power source VBAT, the electric power is consumed by the reference voltage generation circuit 56 and the comparator circuit 57.